Experimental Television Center S-100 Bus and Interface: Schematics, Paul Davis Notes (S-100 Bus Control Signals, Interface Buffer Memory Signals, Interface Connector Signals, and Data Sheets (SSI DM54/DM74 Connection Diagrams/ Gates and One Shots, MSI DM54/DM7489, L89A: 64-Bit Read/Write Memories including General Description, Connection Diagram, and Logic Diagram, similar data for the MSI DM54/DM74154, L154A, LS154: 4-Line to 16-Line Decoders/ Demultiplexers, MSI DM54/DM74157, L157A, S157, LS158, S158: Quad 2-Line to 1-Line Data Selectors/ Multiplexers, MSI DM54/ DM74160A, LS160, 161A, LS161, 162A, LS162, 163A, LS163: Synchronous 4-Bit Counters, MSI DM54/ DM74174, LS174, S174, 175, LS175, S175: Hex/ Quad D Flip-Flops with Clear, Proprietary DM70/ DM8095, L95, 96, L96, 97, L97, 98, L98: TRI-STATE Hex Buffers, Proprietary DM71/ DM8130, 60: Magnitude Comparators, Proprietary DM71/ DM8131, 36: 6-Bit Unified Bus Comparators, Intel Silicon Gate MOS 8102A-4: 1024 Bit Fully Decoded Static MOS Random Access Memory, Line Drivers/ Receivers: DM7837/ DM8837 hex unified bus receiver, and Line Drivers/ Receivers: DM7838/ DM8838 quad unified bus transceiver.